Routing architectures for hierarchical field programmable gate arrays

Author

Aggarwal, Aditya A. ; Lewis, David M.

Author_Institution

Dept. of Electr. Eng., Toronto Univ., Ont., Canada

fYear

1994

fDate

10-12 Oct 1994

Firstpage

475

Lastpage

478

Abstract

This paper evaluates an architecture that implements a hierarchical routing structure for FPGAs, called a hierarchical FPGA (HFPGA). A set of new tools has been used to place and route several circuits on this architecture, with the goal of comparing the cost of HFPGAs to conventional symmetrical FPGAs. The results show that HFPGAs can implement circuits with fewer routing switches, and fewer switches in total, compared to symmetrical FGPAs, although they have the potential disadvantage that they may require more logic blocks due to coarser granularity

Keywords

circuit diagrams; circuit switching; logic arrays; logic design; network routing; HFPGA; coarser granularity; hierarchical FPGA; hierarchical field programmable gate arrays; hierarchical routing structure; logic blocks; routing architectures; routing switches; symmetrical FGPA; Computer architecture; Costs; Delay; Field programmable gate arrays; Logic circuits; Programmable logic arrays; Routing; Switches; Switching circuits; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331954

Filename

331954