• DocumentCode
    2162211
  • Title

    Customized architecture for implementing configurable FFT on FPGA

  • Author

    Chandrakanth, V. ; Tripathi, Shivendra

  • Author_Institution
    Defense R&D Lab.(DRDL), Hyderabad, India
  • fYear
    2013
  • fDate
    22-23 Feb. 2013
  • Firstpage
    1279
  • Lastpage
    1282
  • Abstract
    Fourier transform algorithm has encompassed diverse fields of engineering including specialized fields like radars, communications and image processing systems. Therefore there have been continual efforts to improve the efficiency of FFT implementation in real time systems and other hardware. To reduce design time and time to market, FPGA vendors have developed IP cores which can be readily used in our applications. But these IP core designs though efficient are highly abstract and do not provide the designer to modify them according to his requirement which leads to inefficient design realization. Vendor provided IP cores do not give access to FFT kernel matrix thus restricting the configurability and efficiency of using them. In this paper we have designed a customized architecture to perform FFT with access to twiddle factors for improved configurability. The designed architecture is further modified to perform variable point FFT targeted for application in multirate systems. The architecture designed is generic and can be implemented on any vendor platform.
  • Keywords
    fast Fourier transforms; field programmable gate arrays; logic design; matrix algebra; random-access storage; reconfigurable architectures; storage management; FFT implementation; FFT kernel matrix; FPGA; Fourier transform algorithm; IP core design; RAM; architecture design; communication system; configurability; configurable FFT; customized architecture; design realization; design time; hardware implementation; image processing system; multirate system; radar system; real time system; time to market; twiddle factor; twiddle memory; variable point FFT; vendor platform; Clocks; Computer architecture; Hardware; IP networks; Ports (Computers); Random access memory; Timing; Fast Fourier Transform; Field programmable Gate Arrays; IP core; SAR Image processing; kernel matrix;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advance Computing Conference (IACC), 2013 IEEE 3rd International
  • Conference_Location
    Ghaziabad
  • Print_ISBN
    978-1-4673-4527-9
  • Type

    conf

  • DOI
    10.1109/IAdCC.2013.6514412
  • Filename
    6514412