A self-timed divider using RSD number system

The paper proposes a divider structure that combines a novel self-timed ring structure and a carry-propagation-free division algorithm. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, we can achieve even better performance. A 54-bit divider employing the proposed structure and algorithm was designed with 1.2 μm CMOS technology. We obtained a speed of 215 ns per worst case division on 4.2 mm² of silicon area