Efficient reconfiguration algorithms for degradable VLSI/WSI arrays

A systematic method for reconfiguration in VLSI/WSI (wafer scale integration) arrays using the degradation approach for yield enhancement is presented. Based on the bipartite graph representation of faulty cells in a reconfigurable host array, the problem of finding a maximum fault-free target array is shown to be equivalent to finding a restricted independent set of vertices in the graph models. Three constraints on the row and column reconfigurability are considered. The complexity is analyzed and heuristic algorithms are developed for variations of the problem under the three constraints. These algorithms have been implemented in C and experimental results were collected which demonstrate the efficiency of the proposed approaches