DocumentCode :
2162290
Title :
ARGO: Aging-aware GPGPU register file allocation
Author :
Namaki-Shoushtari, Majid ; Rahimi, Azar ; Dutt, Nikil ; Gupta, Puneet ; Gupta, R.K.
Author_Institution :
Dept. of Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA
fYear :
2013
fDate :
Sept. 29 2013-Oct. 4 2013
Firstpage :
1
Lastpage :
9
Abstract :
State-of-the-art general-purpose graphic processing units (GPGPUs) implemented in nanoscale CMOS technologies offer very high computational throughput for highly-parallel applications using hundreds of integrated on-chip resources. These resources are stressed during application execution, subjecting them to degradation mechanisms such as negative bias temperature instability (NBTI) that adversely affect their reliability. To support highly parallel execution, GPGPUs contain large register files (RFs) that are among the most highly stressed GPGPU components; however we observe heavy underutilization of RFs (on average only 46%) for typical general-purpose kernels. We present ARGO, an Aging-awaRe GPGPU RF allOcator that opportunistically exploits this RF underutilization by distributing the stress throughout RF. ARGO achieves proper leveling of RF banks through deliberated power-gating of stressful banks. We demonstrate our technique on the AMD Evergreen GPGPU architecture and show that ARGO improves the NBTI-induced threshold voltage degradation by up to 43% (on average 27%), that yields improving RFs static noise margin up to 46% (on average 30%). Furthermore, we estimate a simultaneous reduction in leakage power of 54% by providing sleep states for unused banks.
Keywords :
CMOS digital integrated circuits; computer architecture; file organisation; graphics processing units; optimising compilers; parallel processing; power aware computing; AMD Evergreen GPGPU architecture; ARGO; Aging-awaRe GPGPU RF allOcator; GPGPU components; NBTI-induced threshold voltage degradation; RF bank leveling; RF static noise margin; RF stress distribution; aging-aware GPGPU register file allocation; application execution; computational throughput; degradation mechanism; deliberated power-gating; general-purpose graphic processing units; general-purpose kernels; highly parallel execution; highly-parallel application; integrated on-chip resources; leakage power reduction; nanoscale CMOS technology; negative bias temperature instability; register file underutilization; reliability; sleep state; stressful banks; Aging; Degradation; Kernel; Radio frequency; Registers; Resource management; Stress; Aging; GPGPU; NBTI; Power-gating; Register File;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013 International Conference on
Conference_Location :
Montreal, QC
Type :
conf
DOI :
10.1109/CODES-ISSS.2013.6659017
Filename :
6659017
Link To Document :
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