Design of sub-100 nm CMOSFETs: gate dielectrics and channel engineering

Sub-100 nm CMOS transistors with ultra-thin gate dielectrics below 2.0 nm were fabricated and characterized. Super-steep retrograde channel profiles using boron (NMOS) or arsenic (PMOS) channel implantation followed by selective epitaxial growth of undoped-Si were found to effectively reduce short-channel effect and improve current drivability even in the sub-100 nm regime. For NMOS, indium implanted devices showed better short-channel immunity, however, no improvement in current drivability was observed. Optimization of the gate oxide thickness versus gate length was investigated in the presence of direct tunneling leakages and for the first time, an experimental guideline of oxide scaling is proposed. For PMOS, to suppress boron penetration, sub-2.0 nm stack gate dielectrics of oxynitride and LPCVD nitride were developed, which showed excellent transistor characteristics.