Title :
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)
Author :
Zarkesh-Ha, P. ; Meindl, J.D.
Author_Institution :
Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) is presented using the models for global signal, clock, and power supply wiring networks. Based on the models for wiring resource demand, noise limit, and bandwidth requirement, an interconnect design plane is proposed. The new design plane demonstrates the limits imposed on global on-chip interconnect physical dimensions for future technology generations.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; bandwidth requirement; clock; gigascale system-on-a-chip; global interconnects; global on-chip interconnect physical dimensions; global signal; integrated architecture; interconnect design plane; noise limit; power supply wiring networks; wiring resource demand; Bandwidth; Bonding; Clocks; Crosstalk; Power distribution; Power supplies; Power system interconnection; Power system modeling; System-on-a-chip; Wiring;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852822
