Advanced SOI-MOSFETs with strained-Si channel for high speed CMOS-electron/hole mobility enhancement

Author

Mizuno, T. ; Sugiyama, N. ; Satake, H. ; Takagi, S.

Author_Institution

Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

210

Lastpage

211

Abstract

In this work, we propose strained-Si MOSFETs on double-layer SiGe films with different Ge contents as high performance p-MOSFETs. Actually, we demonstrate high hole mobility enhancement (45% against that in control-SOI MOSFETs and 30% against the universal mobility) in strained-SOI p-MOSFETs including double-hetero structures (Si/sub 0.82/Ge/sub 0.18//Si/sub 0.9/Ge/sub 0.1/) for the first time. Moreover, it is also demonstrated that the electron mobility in n-channel strained-SOI MOSFETs is enhanced by about 60%, using single SiGe layer with the Ge content of as low as 10%.

Keywords

MOSFET; electron mobility; hole mobility; silicon-on-insulator; SOI-MOSFET; Si; Si/sub 0.82/Ge/sub 0.18/-Si/sub 0.9/Ge/sub 0.1/; SiGe double heterostructure; double layer film; electron mobility; high speed CMOS; hole mobility; strained Si channel; Annealing; CMOS technology; Capacitive sensors; Charge carrier processes; Electron mobility; Germanium silicon alloys; MOSFET circuits; Silicon germanium; Temperature; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852829

Filename

852829