An ultra compact block cipher for serialized architecture implementations

Author

Wang, Cheng ; Heys, Howard M.

Author_Institution

Electr. & Comput. Eng., Memorial Univ. of Newfoundland, St. John´´s, NL

fYear

2009

fDate

3-6 May 2009

Firstpage

1085

Lastpage

1090

Abstract

In this paper, we present a new block cipher, referred as PUFFIN2, that is designed to be used with applications requiring very low circuit area. PUFFIN2 is designed to be implemented exclusively with CMOS technologies and in a serialized architecture, so that the maximum reuse of hardware components is achieved resulting in a very compact implementation. PUFFIN2 has a block size of 64 bits and a key size of 80 bits. Compared with a serialized implementation of cipher PRESENT, which has the same block size and key size and is claimed as the smallest practical block cipher implementation to date, our cipher has 16% fewer gates using the same CMOS technology. Further, PUFFIN2 inherently supports both encryption and decryption while the serialized PRESENT is an encryption-only implementation.

Keywords

CMOS integrated circuits; application specific integrated circuits; cryptography; CMOS technologies; PUFFIN2; hardware components reuse; serialized architecture; ultra compact block cipher; Application software; Application specific integrated circuits; CMOS technology; Computer architecture; Cryptography; Design engineering; Energy consumption; Hardware; RFID tags; Smart cards; ASIC; block cipher; cryptography; hardware implementation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2009. CCECE '09. Canadian Conference on

Conference_Location

St. John´s, NL

ISSN

0840-7789

Print_ISBN

978-1-4244-3509-8

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2009.5090296

Filename

5090296