Title :
Register estimation from behavioral specifications
Author :
Sharma, Alok ; Jain, Rajiv
Author_Institution :
Hewlett Packard Corp., Roseville, CA, USA
Abstract :
Provides answers to the following problems: (1) Given a data flow graph and a performance constraint, determine a lower-bound on the storage area required for executing the data flow graph while satisfying the performance constraint. (2) Determine a lower-bound on performance for executing a data flow graph under fixed storage area constraints. The results demonstrate that our approach produces solutions which are very close to the optimal
Keywords :
formal specification; graph theory; logic design; performance evaluation; storage allocation; behavioral specifications; data flow graph; fixed storage area constraints; performance constraint; performance lower bound; register estimation; storage area lower bound; Clocks; Costs; Delay estimation; Design optimization; Flow graphs; Optimal scheduling; Processor scheduling; Registers; Scheduling algorithm; Throughput;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331980
