Title :
A CMOS 50% duty cycle repeater using complementary phase blending
Author :
Nakamura, K. ; Fukaishi, M. ; Hirota, Y. ; Nakazawa, Y. ; Yotsuyanagi, M.
Author_Institution :
NEC Corp., Sagamihara, Japan
Abstract :
The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.
Keywords :
CMOS digital integrated circuits; High-speed integrated circuits; Timing circuits; CMOS duty cycle repeater; complementary clock signals; complementary phase blending; symmetrical phase blending inverter; timing skew; Clocks; Degradation; Delay effects; Digital circuits; Impedance; Inverters; MOSFETs; Repeaters; Signal generators; Timing;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852847
