HW/SW co-design architecture exploration for VLSI maze routing

The advance in FPGA technology allowed embedding different types of resources on a single chip. These resources range from a simple look-up table to a complete processor. The resources available on the FPGA fabric allow building various hardware systems for different applications with several trade-offs in terms of performance and power consumption. This paper proposes six different architectures to implement VLSI maze routing algorithm on FPGAs. These architectures utilize two processors (MicroBlaze and Power-PC) and a separate hardware accelerator. The hardware accelerator was designed for the maze routing algorithm with two different protocols for data transfer. All architectures are evaluated based on seven benchmarks. The evaluation includes the performance and the power consumption of the architectures. This work demonstrate that the architecture composed of a soft-core processor directly connected to the hardware accelerator with fully utilized FIFO channel achieves the best power-delay product among all the investigated architectures.