Title :
Performance-constrained parasitic-aware retargeting and optimization of analog layouts
Author :
Liu, Zheng ; Zhang, Lihong
Author_Institution :
Fac. of Eng. & Appl. Sci., Memorial Univ. of Newfoundland, St. John´´s, NL
Abstract :
Performance of analog circuits is highly sensitive to layout parasitics. This paper presents an improved algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. In order to meet the desired circuit specification, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm applies sensitivity-based model to control parasitic-related layout geometries by constructing a set of performance constraints subject to maximum performance deviation due to parasitics. The formulated problem is finally solved using graph-based techniques and nonlinear programming. The algorithm has been demonstrated to be effective and efficient by successfully retargeting several operational amplifiers within minutes of CPU time.
Keywords :
analogue circuits; circuit layout; graph theory; nonlinear programming; analog circuit; analog layouts optimization; graph-based technique; layout parasitics; nonlinear programming; parasitic-related layout geometry; performance-constrained parasitic-aware retargeting; sensitivity-based model; Analog circuits; Automatic control; Circuit optimization; Compaction; Geometry; Integrated circuit interconnections; Manufacturing automation; Parasitic capacitance; Routing; Solid modeling; Analog Circuits; Constraints; Layout Parasitics; Performance Sensitivity; Retargeting;
Conference_Titel :
Electrical and Computer Engineering, 2009. CCECE '09. Canadian Conference on
Conference_Location :
St. John´s, NL
Print_ISBN :
978-1-4244-3509-8
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2009.5090314
