Development of optimum addition algorithm using modified parallel hybrid signed digit (MPHSD) technique

Signed digit (SD) number systems provide the possibility of constant-time addition, where interdigit carry propagation is eliminated. In this paper, two classes of parallel adder are surveyed with an asynchronous adder based on their delay, area and power characteristics. With the development of high speed processors, a tradeoff is always required between area and execution time to yield the most suitable implementation with low power consumption. In this paper, we proposed an optimum high speed fast adder algorithm by using signed and hybrid signed digit algorithms. This modified parallel hybrid signed digit (MPHSD) adder has high speed and less area as compare to conventional adders like ripple carry adder and carry lookahead adder. The MPHSD adder require few more configuration logic blocks (CLB´s) because of redundant logic to optimize execution time with area and power. A relative merits and demerits is also evaluated by performing a detailed analysis in terms of its cost and performance.