Title :
A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel
Author :
Wang, Bo ; Chen, Dianyong ; Liang, Bangli ; Jiang, Jinguang ; Kwasniewski, Tad
Author_Institution :
DOE, Carleton Univ., Ottawa, ON
Abstract :
This paper presents a programmable pre-cursor ISI equalization circuit for high-speed serial data transmission over highly lossy electrical backplane channels. Although decision-feedback-equalizer (DFE) provides an effective way to compensate various channel impairments, such as frequency dependent loss, dispersion and reflections in the legacy backplane environment, for high-speed, highly lossy band-limited channel, the pre-cursor inter-symbol interference (ISI) is still a significant problem for channel equalization. A programmable pre-cursor ISI equalizer combined with a 3-tap DFE is implemented to work at 10-Gb/s and compensate the channel loss of -20 dB. The results show it outperform a traditional 5-tap DFE.
Keywords :
decision feedback equalisers; intersymbol interference; telecommunication links; bit rate 10 Gbit/s; decision-feedback-equalizer; dispersion; frequency dependent loss; high-speed serial transmission link; highly-lossy backplane channel; highly-lossy band-limited channel; intersymbol interference; loss -20 dB; programmable precursor ISI equalization circuit; reflections; Backplanes; Bandwidth; Circuits; Decision feedback equalizers; Distortion; Frequency dependence; Intersymbol interference; Propagation losses; Reflection; Transmitters; Backplane; ISI; SerDes; band-limited channel; decision-feedback equalizer (DFE); equalization; serial link; wireline transceiver;
Conference_Titel :
Electrical and Computer Engineering, 2009. CCECE '09. Canadian Conference on
Conference_Location :
St. John´s, NL
Print_ISBN :
978-1-4244-3509-8
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2009.5090320