Title :
A bit-line leakage compensation scheme for low-voltage SRAM´s
Author :
Agawa, K. ; Hara, H. ; Takayanagi, T. ; Kuroda, T.
Author_Institution :
Syst. ULSI Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
The bit-line leakage current of an SRAM, induced by transistor leakage at low V/sub DD/ and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. By this scheme, V/sub th/ can be lowered to 0.23 V/sub DD/ in a 0.07 /spl mu/m/1.0 V CMOS, as it was before, keeping V/sub th/ and delay scalability of the high-speed SRAM.
Keywords :
CMOS memory circuits; Compensation; High-speed integrated circuits; Leakage currents; Low-power electronics; SRAM chips; 0.07 micron; 0.23 V; 1 V; 320 muA; CMOS static RAM; bit-line leakage compensation scheme; bit-line leakage current; high-speed SRAM; low-voltage SRAM; pre-charge cycle detection; transistor leakage; CMOS technology; Data engineering; Degradation; Delay; Leak detection; Leakage current; Logic circuits; Parasitic capacitance; Random access memory; Ultra large scale integration;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852854
