DocumentCode :
2163590
Title :
A 2.5 V, 20 Gbyte/s 288 M packet-based DRAM with enhanced cell efficiency and noise immunity
Author :
Kyung, K.-H. ; Lee, H.-C. ; Song, K.-W. ; Song, H.-S. ; Jung, K.-W. ; Lee, D.-Y. ; Kim, C. ; Cho, S.-I.
Author_Institution :
Samsung Electron. Co. Ltd., Kyungki, South Korea
fYear :
2000
fDate :
15-17 June 2000
Firstpage :
112
Lastpage :
115
Abstract :
Multimedia and multi-tasking computing systems demand high bandwidth and multi-bank DRAMs. To meet these requirements, several challenges regarding the chip size penalty and noise concerns associated with multi-I/O lines should be resolved. This paper describes a 2.5-V, 288-Mb DRAM with a 32-bank architecture achieving a peak bandwidth of 2.0 GB/s using both 500-MHz differential clocks and 18-I/O organization. This chip features (1) an area- and performance-efficient chip architecture with well-mixed high-speed interface circuits with DRAM peripheral circuits to increase the cell efficiency, (2) a multi-level controlled equalizing scheme and a distributed sense amplifier-driving scheme to enhance the DRAM core timing margin while digressing from the conventional sub-wordline driving scheme, having 352 cells per sub-wordline, (3) an area-efficient column redundancy scheme with multiple fuse-boxes instead of excessive spare memory cell arrays for the multi-I/O architecture, (4) a zero-DC current receiver with a counter kick-back coupling scheme to reduce the reference coupling noise, and (5) a PVT (power, voltage, time) insensitive current control scheme.
Keywords :
Clocks; DRAM chips; Distributed amplifiers; Electric current control; Electric fuses; Equalizers; Multimedia computing; Multiprogramming; Parallel memories; Receivers; Redundancy; Semiconductor device noise; 2.0 GB/s; 2.5 V; 288 Mbit; 500 MHz; DRAM core timing margin; DRAM peripheral circuits; I/O organization; PVT-insensitive current control scheme; area-efficient column redundancy scheme; bandwidth; cell efficiency; chip size penalty; counter kick-back coupling scheme; differential clocks; distributed sense amplifier-driving scheme; high-speed interface circuits; multi-I/O lines; multi-bank DRAM architecture; multi-level controlled equalizing scheme; multi-tasking computing systems; multimedia computing systems; multiple fuse-boxes; noise immunity; packet-based DRAM; performance-efficient chip architecture; reference coupling noise; sub-wordline driving scheme; zero-DC current receiver; Bandwidth; Circuits; Clocks; Computer architecture; Distributed amplifiers; High power amplifiers; Multimedia computing; Multimedia systems; Random access memory; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
Type :
conf
DOI :
10.1109/VLSIC.2000.852865
Filename :
852865
Link To Document :
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