Integration of porous ultra low-k dielectric with CVD barriers

The International Technology Roadmap for Semiconductors predicts the need for ultra low-k dielectric materials combined with very thin barriers on the order of 5 nm total thickness for the use in high performance logic integrated circuits in future technology generations. Some progress has been reported recently regarding the integration of copper with new, relatively weak, ultra low-k materials and the development of new ultra-thin CVD barriers. However there is still considerable concern about the interaction between porous low-k materials and CVD barriers, especially diffusion of CVD precursors into the pores of the low-k material and subsequent metal deposition inside the low-k material. This paper describes the integration of a new CVD barrier with a porous ultra low-k material. First results are discussed for integration into both single and dual damascene structures.