DocumentCode
2163766
Title
1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus
Author
Zerbe, J.L. ; Chau, P.S. ; Werner, C.W. ; Thrush, T.P. ; Perino, D.V. ; Garlepp, B.W. ; Donnelly, K.S.
Author_Institution
Rambus Inc., Mountain View, CA, USA
fYear
2000
fDate
15-17 June 2000
Firstpage
128
Lastpage
131
Abstract
A 1.6 Gb/s/pin 4-PAM multi-drop signaling system has been implemented in 0.35-/spl mu/m CMOS. The system uses current-mode single-ended signaling, with three DC references shared across six I/O pins. A high-gain windowed integrating receiver with wide common-mode range was designed in order to improve SNR when operating with the smaller input overdrive of 4-PAM. Voltage and timing margins are measured via shmoos in a two-drop bussed system.
Keywords
CMOS integrated circuits; Pulse amplitude modulation; Receivers; Telecommunication signaling; Timing; Transmitters; 0.35 micron; 1.6 Gbit/s; 4-PAM signaling; CMOS IC; DC references; SNR improvement; current-mode single-ended signaling; high-gain windowed integrating receiver; multi-drop bus; multi-drop signaling system; wide common-mode range; Attenuation; Circuits; Clocks; Electrostatic discharge; Frequency; Packaging; Pins; Timing; Transmitters; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-6309-4
Type
conf
DOI
10.1109/VLSIC.2000.852869
Filename
852869
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