A selective verify scheme for achieving a 5-MB/s program rate in 3-bit/cell flash memories

Author

Kurata, H. ; Kobayashi, N. ; Kimura, K. ; Saeki, S. ; Kawahara, T.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

2000

fDate

15-17 June 2000

Firstpage

166

Lastpage

167

Abstract

The demand for high density and high-speed programming in flash memories has grown because of audio- and video- storage applications. A multilevel technique is the most effective approach to improving memory density, but it requires precise control of a memory cell´s Vth that doesn´t degrade programming performance. To enable this, we have developed a selective verify scheme for high-speed programming based on simultaneous multilevel programming. A selective verify scheme with asymmetrical cell operation and two-bank operation makes 5-MB/s programming throughput in 3-bit/cell flash memories attainable.

Keywords

Flash memories; PLD programming; Storage management; 3 bit; 3-bit/cell flash memories; 5 MB/s; asymmetrical cell operation; high density high speed programming; memory cell Vth; memory density; multilevel technique; program rate; programming performance; programming throughput; selective verify scheme; simultaneous multilevel programming; two-bank operation; Circuits; Degradation; Flash memory; Laboratories; MOSFETs; Signal generators; Synthetic aperture sonar; Throughput; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6309-4

Type

conf

DOI

10.1109/VLSIC.2000.852880

Filename

852880