Packaging characteristics of 6-layer ultra low-k/Cu dual damascene interconnect featuring advanced scalable porous silica (k=2.1)

Author

Chikaki, S. ; Soda, E. ; Gawase, A. ; Suzuki, T. ; Kawashima, Y. ; Oda, N. ; Saito, S.

Author_Institution

Semicond. Leading Edge Technol., Inc. (Selete), Tsukuba

fYear

2009

fDate

1-3 June 2009

Firstpage

110

Lastpage

112

Abstract

To enhance the process damage tolerance, a 2nd generation scalable porous silica (k=2.1) has been developed by reducing pore-size to 2/3. Using this new low-k film, hybrid dual-damascene interconnects were successfully fabricated with low thermal stress and high adhesion strength. Packaging performance of the six-layered multilevel interconnects was also evaluated with wire-bonding and temperature-cycle tests.

Keywords

adhesion; copper; electronics packaging; integrated circuit interconnections; low-k dielectric thin films; porous materials; silicon compounds; thermal stresses; SiO₂-Cu; adhesion strength; advanced scalable porous silica; hybrid dual-damascene interconnects; low-k film; packaging characteristics; pore size; six-layered multilevel interconnects; temperature-cycle test; thermal stress; ultra low-k-Cu dual damascene interconnect; wire-bonding test; Adhesives; Delamination; Dielectrics; Packaging; Polymers; Silicon compounds; Testing; Thermal expansion; Thermal stresses; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2009. IITC 2009. IEEE International

Conference_Location

Sapporo, Hokkaido

Print_ISBN

978-1-4244-4492-2

Electronic_ISBN

978-1-4244-4493-9

Type

conf

DOI

10.1109/IITC.2009.5090355

Filename

5090355