Optimizing constraints for speed: benchmarking temporal logic

The notion of local constraint processors (“constraint chips”) is introduced. Local constraint processors are defined as hardware chips for processing local (discrete-valued and/or continuous-valued) constraints of arbitrary arity (also referred to as a “constraint class”) in a constraint network. A family of constraint chips supporting temporal scheduling and planning tasks (particularly in the manufacturing domain) is presented. One of these chips/constraint classes is selected (qualitative temporal logic) and compared with an efficient software solution of the same constraint class, with the help of a benchmark family derived from the manufacturing domain. The result shows that constraint chips used as coprocessors generally are faster than efficient software solutions of the same constraint class, but critically depend on the quality of hardware integration into a computer system