A 2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 /spl mu/m CMOS bulk technology

Author

Joshi, R.V. ; Kowalczyk, S.P. ; Chan, Y.H. ; Huott, W.V. ; Wilson, S.C. ; Scharff, G.J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2000

fDate

15-17 June 2000

Firstpage

222

Lastpage

225

Abstract

This paper describes a high speed L1 directory (34 Kb) with read access time below 430 ps and a cycle of 2 GHz in 1.5 V, 0.18 /spl mu/m CMOS bulk technology. The key features of this high performance dynamic design are fast static input/output interface with the provision of converting internal signals from static to dynamic and then back to static at the output, L1/L2 latches at the input, modular building blocks, pseudo-static circuits, robust timing plan and capability for extensive test pattern coverage and access time evaluation using a programmable "Array-Built-In-Self-Test" (ABIST).

Keywords

Built-in self test; CMOS memory circuits; High-speed integrated circuits; Integrated circuit testing; SRAM chips; Timing; 0.18 micron; 1.5 V; 2 GHz; 34 Kbit; 430 ps; CMOS bulk technology; CMOS static RAM; L1 directory SRAM; L1/L2 latches; access time evaluation; built-in-self-test; fast static input/output interface; high performance dynamic design; high speed L1 directory; modular building blocks; programmable array BIST; pseudo-static circuits; robust timing plan; test pattern coverage; CMOS technology; Cache memory; Circuit testing; Clocks; Latches; Logic; Microprocessors; Random access memory; Robustness; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6309-4

Type

conf

DOI

10.1109/VLSIC.2000.852897

Filename

852897