Title :
The scaling of data sensing schemes for high speed cache design in sub-0.18 /spl mu/m technologies
Author :
Zhang, K. ; Hose, K. ; De, V. ; Senyk, B.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Small signal differential data sensing for on-chip cache design is evaluated from the perspective of technology scaling. Maintaining the delay scaling trend and high area efficiency is getting more difficult with the conventional scheme as Si process technology moves beyond 0.18 /spl mu/m. An alternative design scheme with large signal sensing is proposed and proven to be a viable design alternative in the deep sub-micron regime.
Keywords :
CMOS memory circuits; Cache storage; High-speed integrated circuits; Integrated circuit design; 0.18 micron; Si; Si process technology; data sensing schemes; deep submicron regime; differential sensing; high speed cache design; large signal sensing; technology scaling; CMOS technology; Degradation; Delay; Differential amplifiers; Hoses; Integrated circuit interconnections; Microprocessors; Signal design; Signal generators; Voltage;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852898
