A 16 GB/s, 0.18 /spl mu/m cache tile for integrated L2 caches from 256 KB to 2 MB

Author

Miller, J.L. ; Conary, J. ; DiMarco, D.

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2000

fDate

15-17 June 2000

Firstpage

228

Lastpage

231

Abstract

A modular 256 KB advanced transfer cache tile has been developed to implement the on-die second level caches of the 0.18 /spl mu/m Intel(R) Pentium(R) III processor family. The cache tile is stepped from 1 to 8 times to form implementations from 256 KB to 2 MB. Each tile is a self-contained cache delivering a line of 32 B every 2 clock cycles at 1.0 GHz. A charge-share data sense technique overlaps the data and tag array accesses for reduced latency at lower power. Modular tiled cache design also achieves low power through hierarchical power management and reduced test time through PBIST (programmable built in self test).

Keywords

Built-in self test; CMOS memory circuits; Cache storage; High-speed integrated circuits; Integrated circuit testing; Logic testing; Low-power electronics; 0.18 micron; 1 GHz; 16 GB/s; 256 KB to 2 MB; Intel Pentium III processor family; charge-share data sense technique; hierarchical power management; integrated L2 caches; latency reduction; low power operation; modular transfer cache tile; on-die second level caches; programmable BIST; programmable built in self test; test time reduction; Automatic testing; Clocks; Delay; Energy consumption; Energy management; Microprocessors; Phased arrays; Pipelines; Power generation economics; Tiles;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6309-4

Type

conf

DOI

10.1109/VLSIC.2000.852899

Filename

852899