Silicon substrate test structures for hybrid wafer scale technology

The authors explore the variety of test structures that may be used in the fabrication and assembly of silicon substrate multichip modules (MCMs) that aim at wafer scale complexity levels, with particular reference to their technological role. It is pointed out that a comprehensive set of test structures has been devised that provides yield, performance, and reliability information for silicon substrate MCM development activities. Some of these structures are well suited as compact, drop-in process monitors in functional MCM substrate manufacture. Built-in chip self test, scan path interrogation of the on-chip and substrate interconnections for defect location, circuit redundancy, reconfiguration and chip network techniques could all have some place in the realization of advanced MCMs of wafer scale complexity levels