DocumentCode
2164773
Title
The design and implementation of an asynchronous radix-2 non-restoring 32-b/32-b ring divider
Author
Chiang, Jen-Shiun ; Liao, Jun-Yao
Author_Institution
Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
173
Abstract
Division operation is very important in computer systems. Conventionally synchronous techniques are applied to implement the divider. In this paper we propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is simple and is very easy to implement in VLSI. With this asynchronous architecture, we use TSMC´s 0.6 um SPDM process to design a 32-b/32-b radix-2 non-restoring divider. The HSPICE simulation shows that this divider can finish a 32-b/32-b division operation in 3.7 ns to 160.2 ns
Keywords
MOS logic circuits; SPICE; VLSI; asynchronous circuits; dividing circuits; logic CAD; 0.6 micron; 3.7 to 160.2 ns; 32 bit; HSPICE simulation; MOS circuits; SPDM process; TSMC; VLSI; asynchronous radix-2 nonrestoring circuit; ring divider; Asynchronous circuits; Central Processing Unit; Clocks; Computational modeling; Computer architecture; Councils; Delay; Frequency; Process design; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706869
Filename
706869
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