Layout effects on design optimization of CMOS LNA and mixer

Author

Wu, Wen ; Chan, Mansun

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2005

fDate

12-17 June 2005

Abstract

A study on the comparison of different layout methods on the performance of RF CMOS integrated circuits is presented in this paper. Multi-finger and compact waffle layout strategies are investigated in detail. Vital layout parameters, including unit cell configuration and the conflict between finger length and the number of fingers, are analyzed in view of the noise figure and gate RC delay. Layout effects on CMOS LNA and mixer are verified through circuit simulation and fabrication using a 0.35μm standard CMOS process.

Keywords

CMOS analogue integrated circuits; circuit optimisation; integrated circuit layout; low noise amplifiers; mixers (circuits); radiofrequency amplifiers; radiofrequency integrated circuits; 0.35 micron; CMOS low noise amplifiers; CMOS mixers; RF CMOS integrated circuits; compact waffle layout technique; design optimization; integrated circuit layout; multi-finger layout technique; unit cell configuration; CMOS integrated circuits; CMOS process; CMOS technology; Capacitance; Design engineering; Design optimization; Fingers; MOSFETs; Mixers; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2005 IEEE MTT-S International

ISSN

01490-645X

Print_ISBN

0-7803-8845-3

Type

conf

DOI

10.1109/MWSYM.2005.1517153

Filename

1517153