Reliability failure modes in interconnects for the 45 nm technology node and beyond

This work analyses electromigration and dielectric lifetimes of 45 nm node CMOS interconnects. Reliability mechanisms and failure modes are discussed considering, on one hand, the interconnect materials and processes steps, and on the other hand scaling issues. Robust reliability performance meeting the required products target is actually obtained with process integration schemes used for the 45 nm node thanks to fine optimizations of Cu barriers, Cu filling, and ULK surface quality.