CMOS device optimization for mixed-signal technologies

Author

Stolk, P.A. ; Tuinhout, H.P. ; Duffy, R. ; Augendre, E. ; Bellefroid, L.P. ; Bolt, M.J.B. ; Croon, J. ; Dachs, C.J.J. ; Huisman, F.R.J. ; Moonen, A.J. ; Ponomarev, Y.V. ; Roes, R.F.M. ; Da Rold, M. ; Seevinck, E. ; Sreerambhatla, K.N. ; Surdeanu, R. ; Vel

Author_Institution

Philips Res. Leuven, Belgium

fYear

2001

fDate

2-5 Dec. 2001

Abstract

This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario´s for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.

Keywords

CMOS integrated circuits; circuit optimisation; mixed analogue-digital integrated circuits; work function; CMOS device optimization; analog device; asymmetric work function modification; digital device; metal gate integration; mixed-signal technology; system-on-a-chip; technology scaling; CMOS process; CMOS technology; Fasteners; Fluctuations; Implants; Laboratories; Lips; MOS devices; Random access memory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979469

Filename

979469