DocumentCode
2165263
Title
Evaluation of line-edge roughness in Cu/low-k interconnect patterns with CD-SEM
Author
Yamaguchi, Atsuko ; Ryuzaki, Daisuke ; Takeda, Ken´ichi ; Kawada, Hiroki
Author_Institution
Central Res. Lab., Hitachi Ltd., Kokubunji
fYear
2009
fDate
1-3 June 2009
Firstpage
225
Lastpage
227
Abstract
To establish the method for evaluating interconnect LER, resist, low-k, and Cu/low-k samples were observed and electric-field enhancement was simulated. Wedge-shape LER was observed in the edges of low-k and Cu/low-k patterns, and simulations showed that the wedge causes serious electric-field enhancement which can degrade TDDB property. To predict the risk of TDDB, inspections of the wedge angle after low-k etching and Cu CMP are required as well as that of the degree of LER.
Keywords
copper; electric breakdown; integrated circuit interconnections; low-k dielectric thin films; CD-SEM; Cu; Cu/low-k interconnect patterns; LER; TDDB; electric-field enhancement; line-edge roughness; time-dependent dielectric breakdown; wedge angle; Degradation; Electronic mail; Etching; Fluctuations; Histograms; Image edge detection; Inspection; Laboratories; Resists; Scanning electron microscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2009. IITC 2009. IEEE International
Conference_Location
Sapporo, Hokkaido
Print_ISBN
978-1-4244-4492-2
Electronic_ISBN
978-1-4244-4493-9
Type
conf
DOI
10.1109/IITC.2009.5090394
Filename
5090394
Link To Document