Author :
Sleight, J.W. ; Varekamp, P.R. ; Lustig, N. ; Adkisson, J. ; Allen, A. ; Bula, O. ; Chen, X. ; Chou, T. ; Chu, W. ; Fitzsimmons, J. ; Gabor, A. ; Gates, S. ; Jamison, P. ; Khare, M. ; Lai, L. ; Lee, J. ; Narasimha, S. ; Ellis-Monaghan, J. ; Peterson, K. ;
Author_Institution :
Microelectron. Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
This paper describes a second generation 1.2 V high performance 0.13 /spl mu/m SOI technology. Aggressive ground rules and a tungsten damascene local interconnect render the densest 6T 0.13 /spl mu/m SRAM reported to date with a cell area of 1.80 /spl mu/m/sup 2/. 248 nm lithography is used for all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced BEOL process with low-k interlevel dielectrics and SiC barrier layers.
Keywords :
CMOS memory circuits; SRAM chips; copper; dielectric thin films; integrated circuit interconnections; silicon-on-insulator; tungsten; ultraviolet lithography; 0.13 /spl mu/m SOI CMOS technology; 0.13 micron; 1.2 V; 248 nm lithography; 70 nm; 70 nm Si film; Cu; Cu wiring; SRAM; Si-SiO/sub 2/; SiC; SiC barrier layers; W; W damascene local interconnect; aggressive ground rules; cell area; interconnect performance requirements; low-k interlevel dielectrics; second generation low-k Cu BEOL; CMOS technology; Capacitance; Delay; Dielectrics; Hot carriers; MOS devices; Nitrogen; Semiconductor films; Silicon; Threshold voltage;
