Kinetics of C4 bump degradation in overly aggressive HTOL

We will describe the kinetics and mechanism of degradation of flip chip bumps when subjected to overly agressive High Temperature Operational Life tests. Higher temperature is used to shorten the qualification time. Flip Chip bumps degrade when the temperature of the HTOL test exceeds 155 deg.C. The result of this degradation is electrical opens. The root cause of Flip Chip bump failures was investigated. Various device analysis techniques such as FIB, C-SAM, Scanning Auger, EDX and chemical etching were employed to identify the failure location. New techniques were developed to identify the failing interface, which was the Pad Limiting Metallurgy (PLM) between the solder bump and the die. FIB mill techniques were developed and utilized to verify the observed separation on mechanical cross sections. The activation energy of 0.98 eV was estimated using the qualification data. A model was developed describing the chemistry of the aging process at temperature of the HTOL test. It was found that as assembled interface was Cu₃Sn. The mechanical cross sections post HTOL revealed presence of bloating floating intermetallics. In addition the failed units revealed the presence of Cu₆Sn₅ with large grains. This large grain growth at the high temperature is attributed to the aging process. Transformation from Copper rich phase to Tin rich phase forms large voids in the intermetallic. The interfacial void as well as the penetration by solders degrading the integrity of the PLM caused electrical opens. Based on the 0.98 eV activation energy, the HTOL test temperature was reduced to a lower temperature. Extensive testing at this lower temperature has shown no electrical problems due the degradation of the interface