A current-mode approach to CMOS neural network implementation

Author

Watanabe, K. ; Wang, L. ; Cha, H.-W. ; Ogawa, S.

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan

fYear

1997

fDate

10-12 Dec 1997

Firstpage

625

Lastpage

637

Abstract

CMOS equivalents of the synapse and the neuron are proposed for LSI implementation of an adaptive analog neural network. The synapse is a multiplying digital-to-analog converter based on an R-2R ladder and the neuron consists of the second-generation current conveyor. Prototype chips fabricated independently using 0.6 μm CMOS process have confirmed the wideband signal processing capability owing to a fully current-mode approach. Detailed analyses of measured performances have also given the design criteria for fully parallel implementation

Keywords

CMOS analogue integrated circuits; digital-analogue conversion; large scale integration; neural chips; parallel architectures; signal processing; CMOS neural network; LSI implementation; R-2R ladder; adaptive analog neural network; current-mode approach; multiplying digital-to-analog converter; neuron; parallel implementation; performance; second-generation current conveyor; synapse; wideband signal processing; Adaptive signal processing; Adaptive systems; CMOS process; Digital-analog conversion; Large scale integration; Neural networks; Neurons; Performance analysis; Prototypes; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Algorithms and Architectures for Parallel Processing, 1997. ICAPP 97., 1997 3rd International Conference on

Conference_Location

Melbourne, Vic.

Print_ISBN

0-7803-4229-1

Type

conf

DOI

10.1109/ICAPP.1997.651528

Filename

651528