Data retention time in DRAM with WSi/sub x//P/sup +/poly-Si gate NMOS cell transistors

A 64-Mbit DRAM with WSi/sub x//P/sup +/poly-Si gate NMOS cell transistors (P+gate DRAM) has been developed to improve the DRAM data retention time of the tail-distribution. The data retention time that corresponds to 0.01% failure bit in the cumulative probability of the P+gate DRAM is 2.7 times longer than that of conventional N+gate DRAMs. The main reason for the improved data retention time is that the low channel-doping level, achieved by the P+gate DRAM, reduces the electric field at around 0.04 /spl mu/m depth below the surface.