Board level reliability of a waferlevel CSP using stacked solder spheres and a solder support structure (S3)

Developing a CSP at waferlevel is a challenging task with respect to board level reliability. Board level reliability should be achieved in contrast to flip chip technology without underfilling. Of course the target of a CSP manufacturing technology at waferlevel is cost reduction. The S³-Diepack is a waferlevel CSP developed at the Technical University of Berlin within the European ESPRIT project ESCHETA. The S³-Diepack uses a redistribution layer to a achieve a standardized I/O-array and stacked solder spheres with a solder support structure (S³) to improve board level reliability. The S³-Diepack used in this investigation has a size of 10 mm×10 mm, 196 I/O´s and a pitch of 0.5 mm. Due to the stacked solder spheres a stand-off height of about 0.4 mm is achieved after assembly. 1000 cycles -40 to +100°C have been achieved on a thin FR5 board before electrical failure. Over 750 cycles -55 to +125°C were passed on thick FR4 board