A Built-In Self-Test Scheme for Soft Error Rate Characterization

Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for extended period of time. While built-in self-test (BIST) mechanisms have been around for over a decade, that minimizes the use of a tester; they have not been applied to measure or characterize soft error rate. This is because traditional BIST methods cannot distinguish between a soft failure and a hard failure and have no provision for counting the number of errors. In this paper, we propose a BIST design for soft error rate (SER) characterization, which obviates those issues. The proposed BIST based SER measurement scheme can be further accelerated by improved controllability and observability while unlike traditional BIST schemes, a test by test failure detection capability enables higher diagnostic resolution for single event based transient errors. We further propose to integrate this chip-level BIST-based SER characterization system with a distributed on-line scheme using a network controller that tests multiple chips in parallel and completely eliminates the need for a tester. The hardware overhead of the proposed architecture is small and it becomes insignificant for larger design.