Title :
Sub-20 nm CMOS FinFET technologies
Author :
Yang-Kyu Choi ; Lindert, N. ; Peiqi Xuan ; Tang, S. ; Daewon Ha ; Anderson, E. ; Tsu-Jae King ; Bokor, J. ; Chenming Hu
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.
Keywords :
CMOS integrated circuits; MOSFET; chemical vapour deposition; electron beam lithography; nanotechnology; 20 nm; Ge; drive current; e-beam lithography; fabrication process; manufacturable process; nanoscale CMOS; overlap capacitance; parasitic series resistance; patterning approaches; raised S/D structures; selective Ge LPCVD; spacer lithography; sub-20 nm CMOS double-gate FinFETs; CMOS process; CMOS technology; Etching; Fabrication; FinFETs; Lithography; Manufacturing processes; Parasitic capacitance; Space technology; Thermal stresses;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979526
