Title :
High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices
Author :
Kedzierski, J. ; Fried, D.M. ; Nowak, E.J. ; Kanarsky, T. ; Rankin, J.H. ; Hanafi, H. ; Natzle, W. ; Boyd, D. ; Ying Zhang ; Roy, R.A. ; Newbury, J. ; Chienfan Yu ; Qingyun Yang ; Saunders, P. ; Willets, C.P. ; Johnson, A. ; Cole, S.P. ; Young, H.E. ; Car
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.1 V, with off-currents less than 100 nA/um at V/sub gs/=0.
Keywords :
CMOS logic circuits; MOSFET; elemental semiconductors; high-speed integrated circuits; silicon; 0.1 V; FinFET devices; Si; asymmetric-gate devices; double-gate FinFET devices; drain currents; fully optimized technologies; off-currents; polysilicon gates; symmetric-gate devices; CMOS logic circuits; Epitaxial growth; Etching; FinFETs; Implants; Logic devices; MOS devices; MOSFETs; Microelectronics; Silicon;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979530
