Title :
Ultrathin high-K gate stacks for advanced CMOS devices
Author :
Gusev, E.P. ; Buchanan, D.A. ; Cartier, E. ; Kumar, A. ; DiMaria, D. ; Guha, S. ; Callegari, A. ; Zafar, S. ; Jamison, P.C. ; Neumayer, D.A. ; Copel, M. ; Gribelyuk, M.A. ; Okorn-Schmidt, H. ; D´Emic, C. ; Kozlowski, P. ; Chan, K. ; Bojarczuk, N. ; Ragnar
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.
Keywords :
CMOS integrated circuits; carrier mobility; dielectric thin films; integrated circuit reliability; leakage currents; sputter deposition; vapour deposition; 1000 degC; Al/sub 2/O/sub 3/; AlN/sub y/(O/sub x/); CMOS devices; HfO/sub 2/; HfO/sub 2/-Al/sub 2/O/sub 3/; ZrO/sub 2/; channel mobility; charge trapping; deposition techniques; device characteristics; dielectric integration; flatband voltage shifts; gate dielectrics; gate leakage currents; oxide reliability; ultrathin high-K gate stacks; CMOS process; Crystalline materials; Current measurement; Dielectric materials; High K dielectric materials; High-K gate dielectrics; Leakage current; Silicon; Thermal stability; Voltage;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979537
