DocumentCode
2166690
Title
Yield Improvement, Fault-Tolerance to the Rescue?
Author
Vial, J. ; Bosio, A. ; Girard, P. ; Landrault, C. ; Pravossoudovitch, S. ; Virazel, A.
Author_Institution
CNRS, Univ. Montpellier II, Montpellier
fYear
2008
fDate
7-9 July 2008
Firstpage
165
Lastpage
166
Abstract
With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.
Keywords
fault tolerance; integrated circuit reliability; integrated circuit yield; redundancy; fault tolerance; fault tolerant architectures; manufacturing defects; triple modular redundancy architecture; yield improvement; Circuit faults; Fault tolerance; Fault tolerant systems; Hardware; Manufacturing processes; Redundancy; Robots; Testing; Uniform resource locators; Very large scale integration; Fault-tolerance; TMR; manufacturing defects; test of tolerant architecture; yield ramp-up;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
Conference_Location
Rhodes
Print_ISBN
978-0-7695-3264-6
Type
conf
DOI
10.1109/IOLTS.2008.10
Filename
4567080
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