• DocumentCode
    2166932
  • Title

    Self-reconfigurable algorithm of WSI sorting network

  • Author

    Horiguchi, Susumu ; Numata, Issei ; Kimura, Masayuki

  • Author_Institution
    Dept. of Inf. Sci., Tohoku Univ., Sendai, Japan
  • fYear
    1991
  • fDate
    29-31 Jan 1991
  • Firstpage
    249
  • Lastpage
    255
  • Abstract
    The authors present a self-reconfigurable algorithm for a hierarchically redundant WSI (wafer scale integration) sorting network. This WSI sorting network consists of a mesh interconnection and a modified bitonic sorter with spare cells. The fault tolerance performance of the WSI sorting network using the self-reconfigurable algorithm is discussed. It is confirmed that the hierarchical redundancy of the WSI sorting network achieves a higher fault tolerance performance than a nonhierarchical network and is suitable for both clustered faults and random faults
  • Keywords
    VLSI; fault tolerant computing; microprocessor chips; parallel processing; sorting; WSI sorting network; clustered faults; fault tolerance performance; hierarchical redundancy; hierarchically redundant WSI; mesh interconnection; modified bitonic sorter; random faults; self-reconfigurable algorithm; spare cells; wafer scale integration; Application software; Circuits; Concurrent computing; Fault tolerance; Power engineering computing; Redundancy; Sorting; Systolic arrays; Very large scale integration; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-8186-9126-3
  • Type

    conf

  • DOI
    10.1109/ICWSI.1991.151723
  • Filename
    151723