DocumentCode
2167132
Title
A 32-nm CMOS Frequency Locked Loop for 20-GHz Synthesis with ± 7.6 ppm Resolution
Author
Bousquet, J.-F. ; Aouini, Sadok ; Ben-Hamida, Naim ; Wolczanski, John
Author_Institution
Electr. & Comput. Eng., Dalhousie Univ., Halifax, NS, Canada
fYear
2013
fDate
13-16 Oct. 2013
Firstpage
1
Lastpage
4
Abstract
In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS technology and acts as a 20-GHz frequency synthesizer. The frequency difference between the reference clock and the VCO output is obtained using a pair of 18- bit counters. Also, an offset value is added to the counter output to tune the VCO frequency in closed loop. The frequency synthesizer resolution is ± 7.6 p.p.m. over a measured locking range equal to 300 MHz.
Keywords
CMOS digital integrated circuits; frequency locked loops; frequency synthesizers; voltage-controlled oscillators; CMOS frequency locked loop; VCO output; counter output; digitally assisted frequency locked loop; frequency 20 GHz; frequency synthesizer; offset value; reference clock; size 32 nm; word length -18 bit; Charge pumps; Clocks; Frequency locked loops; Frequency modulation; Radiation detectors; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2013 IEEE
Conference_Location
Monterey, CA
Type
conf
DOI
10.1109/CSICS.2013.6659192
Filename
6659192
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