Soft-Error Vulnerability of Sub-100-nm Flip-Flops

Author

Heijmen, Tino

Author_Institution

NXP Semicond., Eindhoven

fYear

2008

fDate

7-9 July 2008

Firstpage

247

Lastpage

252

Abstract

The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate estimation of the contribution of flip-flops to the SER of an IC. The method is applicable to frequencies well below 1 GHz. The approach is based on a set of expressions for the timing vulnerability factor (TVF) of the master and slave latches of the flip-flop. With this approach it is possible to make an accurate estimation of the flip-flop SER parameters.

Keywords

flip-flops; integrated circuit reliability; integrated circuit testing; SER sensitivity; alpha-accelerated testing; flip-flops; master latches; slave latches; soft-error rate; soft-error vulnerability; timing vulnerability factor; CMOS integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Flip-flops; Frequency estimation; Latches; Master-slave; Random access memory; Timing; SER; flip-flops; soft errors; sub-100-nm CMOS; timing vulnerability factors;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International

Conference_Location

Rhodes

Print_ISBN

978-0-7695-3264-6

Type

conf

DOI

10.1109/IOLTS.2008.12

Filename

4567102