Meeting the heat removal requirements of `tiled´ compliant wafer level packages

The `tiling´ of wafer level packages yields the maximum increase in the performance and the packing efficiency. The limitations on the `tiling´ are posed by the capability of removing the heat from all the applications ranging from low power to high power. This paper presents a thorough analysis of the optimum thermal design of the wafer level package and the system assembly to meet the high performance heat removal requirements while maintaining the `tiled´ assembly. The results indicate that even with heat sink fin aspect ratio of 100:1, it is not possible to remove the heat from the `tiled´ high performance wafer level package assembly. An optimum methodology is developed to determine the placement of components on the beard such that the heat can be removed without sacrificing the `tiled´ assembly. By using this methodology, the fin aspect ratio of 25 and 50 is sufficient to meet the cost performance and high performance applications´ heat removal requirements, respectively