A DSP realization of a CELP testbench

Author

Wong, T. ; Gargour, C. ; Batani, N.

Author_Institution

Ecole de Technol. Superieure, Quebec Univ., Montreal, Que., Canada

fYear

1993

fDate

14-17 Sep 1993

Firstpage

167

Abstract

A testbench which enables a software implementation of different code-excited linear predictive (CELP) coder configurations in a simple and modular way, is presented as a research and development tool. It permits a flexible simulation process while using the actual hardware and software resources which constitute a real system. Its behaviour is consequently close to that of the final system envisaged. This testbench has been developed using the TMS320C30 digital signal processor and has been programmed in a modular way in C language. A CELP coder using two different codeword generation methods (the LBG algorithm and the Fuzzy-LVQ partitioning algorithm) have been tested using the proposed testbench

Keywords

digital signal processing chips; digital simulation; linear predictive coding; C language; CELP coder configurations; CELP testbench; DSP realization; Fuzzy-LVQ partitioning algorithm; LBG algorithm; TMS320C30 digital signal processor; code-excited linear predictive coder configurations; codeword generation methods; simulation process; software implementation; software resources; Digital signal processing; Digital signal processors; Filters; Hardware; Partitioning algorithms; Predictive models; Signal processing algorithms; Signal synthesis; Speech synthesis; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1993. Canadian Conference on

Conference_Location

Vancouver, BC

Print_ISBN

0-7803-2416-1

Type

conf

DOI

10.1109/CCECE.1993.332209

Filename

332209