Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology

Author

Ker, Ming-Dou ; Chen, Tung-Yang ; Wu, Chung-Yu ; Tang, Howard ; Su, Kuan-Cheng ; Sun, S.W.

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

212

Abstract

A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 Å) of the input stage in a 0.25 μm CMOS technology and sustain an ESD level above 2000 V without extra process modification

Keywords

CMOS integrated circuits; electrostatic discharge; isolation technology; protection; 0.25 micron; 2000 V; 50 A; ESD robustness improvement; deep-submicron CMOS technology; input ESD protection circuit; shallow-trench-isolation CMOS technology; substrate-triggering technique; thin gate oxide; trigger voltage reduction; Atherosclerosis; Breakdown voltage; CMOS integrated circuits; CMOS technology; Electrostatic discharge; Laboratories; MOS devices; Protection; Resistors; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706879

Filename

706879