Title :
Yield learning and volume manufacturing of high performance logic technologies on 200 mm and 300 mm wafers
Author :
Gasser, R.A., Jr.
Abstract :
This paper describes the rapid yield learning and high volume ramp of Intel´s 130 nm logic technology on both 200 mm and 300 mm wafers. This process technology delivers industry leading performance, yield, reliability and density that is matched on both 200 mm and 300 mm wafers. This technology supports SRAM cell sizes down to 2 /spl mu/m/sup 2/ and has produced >10 M high speed microprocessors at the time of this publication.
Keywords :
CMOS digital integrated circuits; design for manufacture; integrated circuit manufacture; integrated circuit reliability; integrated circuit yield; statistical process control; 130 nm; 200 mm; 200 mm wafers; 300 mm; 300 mm wafers; CMOS transistor performance; Copy Exactly transfer methods; Intel 130 nm logic technology; SRAM cell sizes; high performance logic technologies; high speed microprocessors; high volume ramp; process design for manufacturing; rapid yield learning; reliability; statistical process control capability; volume manufacturing; Chemical technology; Chemistry; Copper; Isolation technology; Logic; Manufacturing industries; Manufacturing processes; Process design; Random access memory; Transistors;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979576
