A 50 nm depleted-substrate CMOS transistor (DST)

In this paper we show a Depleted-Substrate Transistor (DST) technology which demonstrates significant performance gain over bulk Si transistors without the floating body effect (FBE). We have fabricated depleted-substrate CMOS transistors on thin silicon body (/spl les/30 nm) with physical gate lengths down to 50 nm which show much steeper subthreshold slopes (/spl les/75 mV/decade) and improved DIBL (/spl les/50 mV/V) over both partially-depleted (P-D) SOI and bulk Si, for both PMOS and NMOS transistors. The salicide formation and high parasitic resistance problems associated with the use of thin Si body can be overcome by using raised source/drain. Depleted-substrate PMOS transistors with 50 nm physical gate length and raised source/drain were fabricated and achieved I/sub on/=0.65 mA/um and I/sub off/=9 nA/um at V/sub cc/=1.3 V. This PMOS drive current is the highest ever reported, and is about 30% higher than any previously published PMOS I/sub on/ value for both PD-SOI and bulk Si at a given I/sub off/. The use of raised source/drain improved the I/sub on/ of the depleted-substrate NMOS transistors by /spl sim/20%. Depleted-substrate NMOS transistors with 65 nm physical gate length and raised source/drain achieved DIBL=45 mV/V, subthreshold slope=75 mV/decade, I/sub on/=1.18 mA/um and I/sub off/ =60 nA/um at V/sub cc/=1.3 V, as well as significant improvement in Id-Vd characteristics due to a 60% reduction in DIBL and >25% improvement in subthreshold slope over the bulk Si.