DocumentCode
2167760
Title
CSP assembly reliability and effects of underfill and double-sided population
Author
Ghaffarian, R.
Author_Institution
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA
fYear
2000
fDate
2000
Firstpage
390
Lastpage
396
Abstract
The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. In the process of building the Consortium CSP many challenges were identified regarding aspects of technology implementation. Last year, ball shear test results before and after isothermal aging were presented and compared to ball grid array packages. These package were assembled on single- and double sided printed circuit board (PWB) without and with underfill. These test vehicles are subjected to various environmental tests including four thermal cycling conditions. These cycles represent the extreme harsh accelerated testing in the range of -55 to 125°C to a commercial requirement in the range of 0 to 100°C. This paper presents the thermal cycling test results to 2,000 cycles performed under different environmental conditions for single- and double-sided assemblies with and without underfill
Keywords
chip scale packaging; encapsulation; integrated circuit reliability; microassembling; -55 to 125 C; 0 to 100 C; accelerated testing; chip scale package; double-sided assembly; harsh environment; printed circuit board; reliability; single-sided assembly; thermal cycling; underfill; Aging; Assembly; Chip scale packaging; Circuit testing; Companies; Electronics packaging; Government; Isothermal processes; Printed circuits; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th
Conference_Location
Las Vegas, NV
Print_ISBN
0-7803-5908-9
Type
conf
DOI
10.1109/ECTC.2000.853183
Filename
853183
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